Replying to @CppGuy@infosec.space
@CppGuy it’s good news and bad news. The good news: CISC architecture CPUs run their own firmware/microcode to implement a lot of that complexity, and some vulnerabilities can be patched. The bad news: RISC architectures tend not to, thus any chip-level vulnerabilities need a hardware fix.
As an engineer, I tend to the view that the more complex a system or component is, the more failure modes it’s got. Give me RISC any day. To be even more specific, give me ARM 😎