Well, there is a problem with the HDMI clock out from the FPGA - weird repeating pattern.
I use a 4th LVDS DDR geared lane and stuff it with 1's or 0's on alternating 1/5 DDR clock signal. I might have my math wrong I'll need to double check here.
Blue is 56MHz generated from SDR debug pin, and green is measured with diff probe on 560Mhz LVDS out. They should match.
Replying to @0h00000000@ioc.exchange
I might just try using a divided x10 clock out of the PLL instead of generating based on the div5 clock from the DDR gearing IP. They should line up. Probably... Likely... Right?
Replying to @0h00000000@ioc.exchange
@0h00000000 Also check clocks going into your SERDES and make sure they're proper frequencies/phases. I've had all manner of problems when my slow and fast domains weren't the right multiple or misaligned or something
Replying to @azonenberg@ioc.exchange
@azonenberg Yeah, there is weirdness happening on a rotating basis and also during hsync events, no bueno for the clock. I was trying to use a single 4 lane LVDS bus instead of 4 single lanes to minimize all the rest logic and minimize skew.