Ben

Well crap, I don't have any monitors that can accept 1080p24, they all want a 60hz or better refresh rate. I'm limited to a 62.5Mhz pixel clock. It looks like 800x600 is the best I can do with what I have, and that will let me validate that my HDMI logic is working.

The smaller BGA121 package would let me do 1500Mbps - or a 75Mhz pixel clock. I really need something with a SERDES interface(s), then I could just do display port over one lane. All those FPGAs need a paid version of the Lattice software though. Doh!

I'll screw with it in the morning. Time for the gym.

I wasn't getting signal out of the re-drivers, and I tried everything, for hours. And then I realized I had the I2C addresses swapped for the 2 redrivers, so I was talking to the one I wasn't using.

Now I've got signal after the driver, but monitor isn't syncing up. I'm gonna try swapping some bits on the data lanes around like I had them originally.

@craigjb https://www.youtube.com/watch?v=PmZFGw5CeWE

Ok, that's better. A bit skewed, but I haven't added any constraints. Now I need to check that I have the redriver configured for right pin order, and then look at my data lanes again.

Crap. I've been measuring the wrong diff pair thinking it was clk when it wasn't.

Ugh.

@azonenberg Yeah, there is weirdness happening on a rotating basis and also during hsync events, no bueno for the clock. I was trying to use a single 4 lane LVDS bus instead of 4 single lanes to minimize all the rest logic and minimize skew.

I might just try using a divided x10 clock out of the PLL instead of generating based on the div5 clock from the DDR gearing IP. They should line up. Probably... Likely... Right?

Well, there is a problem with the HDMI clock out from the FPGA - weird repeating pattern.

I use a 4th LVDS DDR geared lane and stuff it with 1's or 0's on alternating 1/5 DDR clock signal. I might have my math wrong I'll need to double check here.

Blue is 56MHz generated from SDR debug pin, and green is measured with diff probe on 560Mhz LVDS out. They should match.

OMG - I FINALLY got the I2C to the HDMI re-drivers working. I took an hour off to go watch the fireworks and then came back and locked in.

There were two main issues. First the MUX needed > 2.5v. Secondly, the EN pins had a 250k internal pull up, but when I measured them they were 0V. It turns out I tied them to extra FPGA pins in case I wanted to control them. The FPGA was uninitialized and pulling them down.

Then I had one of the addresses wrong. But finally, the thing that should be UBER simple to get working, is working.

I'll try configuring them tomorrow and see if I get a HDMI signal out of them.

@azonenberg 👏 🍻

@smellsofbikes I usually use some UV cure epoxy. In this case the clearance between 1v8 and 3ve rails is super close, so that's my main concern.

The hot glue tip is handy, but then I have hot glue on the tip of my soldering iron.

I’ll need to add some epoxy later, but this was easier than expected.

Crap - I have a MUX for I2C for the HDMI drivers, and I routed 1V8 for VCC, but the datasheet says 2.5V minimum.

It's a tiny package, but the rework is doable, the complicating factor is the million things I have hooked up to it for debugging.

@azonenberg In Texas we have Bucee's - they've now expanded to 13 states and the biggest store is in Luling, TX on I10 - 75,000 sq ft with 120 gas pumps. They have a fudge stand, a jerkey counter, a BBQ section and every bagged snack you could think of. Oh, and their claim to fame - clean bathrooms.

https://www.youtube.com/watch?v=md17vkwMxww